publication venue for

• Intelligent Sensing and Classification in DSR-Based Ad Hoc Networks 2009
• Failure trace analysis of timed circuits for automatic timing constraints derivation 2005
• Partial order reduction for detecting safety and timing failures of timed circuits 2005
• Framework of timed trace theoretic verification revisited 2002
• A conservative framework for safety-failure checking 2006
• Partial order reduction for timed circuit verification based on level oriented model 2002